1. Field of the Invention
The invention relates generally to a method of erasing flash memory cells, and more particularly to, a method of erasing flash memory cells by which a recovery operation and an erase operation are simultaneously performed by changing a method of discharging the flash memory after the memory is erased.
2. Description of the Prior Art
Generally, in a flash memory, in order to make constant distribution of the threshold voltage (Vt) upon an erase operation, a pre-program operation is first performed to set the threshold voltages of the cells to be erased and an erase operation is then performed. After the erase operation is performed, a post-program and a recovery operation are performed so that the cells that may have been over erased are converged to have a constant threshold voltage.
A conventional method of erasing the flash memory will be described by reference to FIG. 1.
FIG. 1 is flowchart for explaining the conventional method of erasing the flash memory cells. A pre-program operation for increasing the threshold voltage of each of the cells by programming the cells in a selected block (eleventh step) and a verify operation are performed (twelfth step), before the erase operation for the flash memory device is performed. The pre-program operation is performed for the purpose of preventing a phenomenon that the cells are over erased since most of the already-erased cells have further low threshold voltages if these cells are again erased. After the verify operation, the threshold voltages of the entire cells are adjusted and are erased in a block unit (thirteenth step). Next, the erase state is verified (fourteenth step). As a result of verification, if erase is not sufficient, the erase operation is again performed. This series of the operations are repeated. After all the cells are erased, in order to solve the over-erasing problem for some cells having an erase characteristic of a relatively fast speed, the recovery operation for preventing a leakage current by mean of some programming operation (fifteenth step) and the verify operation are performed (sixteenth step), thus completing the erase operation for the flash memory device.
During the erase operation (thirteenth step) and the verify operation (fourteenth), if the cells having the erase characteristic of a low speed do not fall below a given threshold voltage (for example, 2V), erase pulses are applied to all the cells. At this time, the cells having a fast erase characteristic are over erased. If the leakage currents of the over-erased cells are over an allowable level, the threshold voltage of the cells can be increased in the recovery operation. However, if the leakage currents are over the allowable limit, these chips are a fail. Fail of the recovery operation in the flash memory is the most important problem in decreasing the yield.
The conventional method of erasing the flash memory cells will be explained in further detail.
FIG. 2 is a cross sectional view of the flash memory cell for explaining the conventional method of erasing the cell. The flash memory cell includes a semiconductor substrate 20, a source region 22, a drain 24, a floating control gate 26 and a control gate 28. At this time, for convenience of explanation, it is assumed that a voltage applied to the substrate is Vb, and voltages applied to the source, the drain and the control gate are VS, VD and Vg, respectively.
First, in order to erase the cells of the flash memory, xe2x88x928V is applied to Vg and 8V is applied to Vb. Then, electric charges within the floating control gate 26 exit in the substrate 20 by means of a F-N tunneling method. At this time, if the source 22 and the drain 24 are floated, the substrate is a P type and a junction is an N type, a voltage of about 7.3V is actually applied to the source and the drain since the substrate and the junction are in a forward bias state. Thereafter, after the erase operation is completed, a discharge operation is performed. First, in a state that the control gate is grounded, Vg is discharged to 0V and Vb is also discharged to 0V.
Next, if the erase operation for the flash memory cell is finished, the recovery operation is performed. Upon the recovery operation, Vg, Vb and VS are grounded and 5V is applied to VD, so that the over-erased cells are converged to have a constant threshold voltage.
The present invention is contrived to solve the above problems and an object of the present invention is to provide a method of erasing flash memory cells by which a recovery operation and an erase operation are simultaneously performed so that the cells are converged to have a constant threshold voltage, by changing a method of discharging the flash memory after the memory is erased.
In order to accomplish the above object, a method of erasing the flash memory cell having a substrate, a source, a drain, a tunnel oxide film, a floating gate, a dielectric film and a control gate according to the present invention, is characterized in that it comprises the steps of performing an erase operation for the cell, by applying a negative voltage being an erase voltage to the control gate and a positive voltage being an erase voltage to the substrate, discharging the control gate by making the control gate grounded, discharging the source by making the source grounded, and simultaneously performing a discharge operation and a recovery operation by making the substrate grounded.
In order to accomplish the above object, a method of erasing the flash memory cell having a substrate, a source, a drain, a tunnel oxide film, a floating gate, a dielectric film and a control gate according to the present invention, is characterized in that it comprises the steps of performing an erase operation for the cell by applying a negative voltage being an erase voltage to the control gate, a positive voltage being an erase voltage to the source and the drain and making the substrate grounded, discharging the control gate by making the control gate grounded, and discharging the source and drain voltages toward the source and by making the source grounded and simultaneously performing a recovery operation for the cell.